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FEATURES Significant Performance Advantages over LF155 and LF157 Devices Low Input Offset Voltages: 500 V Max Low Input Offset Voltage Drift: 2.0 V/ C Minimum Slew Rate Guaranteed on All Models Temperature-Compensated Input Bias Currents Bias Current Specified Warmed-Up Over Temperature Internal Compensation Low Input Noise Current: 0.01 pA//Hz / High Common-Mode Rejection Ratio: 100 dB Models with MIL-STD 883 Processing Available OP15 156 Speed with 155 Dissipation: 80 mW Typ Wide Bandwidth: 6 MHz High Slew Rate: 13 V/ s Fast Settling to 0.1%: 1,200 ns OP17 Highest Slew Rate: 60 V/ s Fastest Settling to 0.1%: 600 ns Highest Gain Bandwidth Product (AVCL = 5 Min): 30 MHz Guaranteed Input Bias Current @ 125 C
Precision JFET-Input Operational Amplifiers OP15/OP17
GENERAL DESCRIPTION
The ADI-JFET input series of devices offer clear advantages over industry-generic devices and are superior in both cost and performance to many dielectrically-isolated and hybrid op amps. All devices offer offset voltages as low as 0.5 mV with TCVOS guaranteed to 5 mV/C. A unique input bias cancellation circuit reduces the IB by a factor 10 over conventional designs. In addition ADI specifies IB and IOS with the devices warmed up and operating at 25C ambient. These devices were designed to provide real precision performance along with high speed. Although they can be nulled, the design objective was to provide low offset-voltage without nulling. Systems generally become more cost effective as the number of trim circuits is decreased. ADI achieves this performance by use of an improved bipolar compatible JFET process coupled with on chip, zener-zap offset trimming. The OP15 provides an excellent combinations of high speed and low input offset voltage. In addition, the OP15 offers the speed of the 156A op amp with the power dissipation of a 155A. The combination of a low input offset voltage of 500 mV, slew rate of 13 V/ms, and settling time of 1,200 ns to 0.1% makes the OP15 an op amp of both precision and speed. The additional features of low supply current coupled with an input bias current makes the OP15 ideal for a wide range of applications. The OP17 has a slew rate of 60 V/ms and is the best choice for applications requiring high closed-loop gain with high speed. See OP42 datasheet for unity gain applications and the OP215 datasheet for a dual configuration of the OP15.
V+ Q5
J5
R8* NULL
J8
R7* NULL Q16
*R7, R8 ARE ELECTRONICALLY ADJUSTED ON CHIP FOR MINIMUM OFFSET VOLTAGE.
Q6 R3 Q8 J11 NONINVERTING INPUT J1 J2 -INV INPUT Q1 Q3 Q12 Q7
Q9
J6
Q19 Q24
R1
Q17 R2 C2 Q2 Q4
R13
Q22
OUTPUT Q10 J10 Q23 J9
Q11 J3 C1 7.4pF J4 R3 R4
R5 3.6k Q16
Q13
R6 3.6k Q15
Q14
Q20
Q25
Q21
R11
V-
Figure 1. Simplified Schematic
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
OP15/OP17-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V =
S
15 V, TA = 25 C, unless otherwise noted)
OP15A, OP15E OP17A, OP17E Min Typ Max 0.2 3 5 3 5 15 18 15 20 1012 0.5 10 22 10 25 50 110 50 130 OP15F OP17F Typ 0.4 6 10 6 10 30 40 30 40 1012 75 12 11 4.0 7.0 7.5 35 3.5 15 220 13 12.7 2.7 4.6 11 50 5.7 28 13 10 4.5 1.5 1.2 1.5 0.7 0.6 10.5 100 10 20 15 0.01 0.01 3 51 86 100 82 10 20 15 0.01 0.01 3 51 10 20 15 0.01 0.01 3 80 96 10.3 4.0 7.0 5 25 3.0 11 50 12 11 OP15G OP17G Typ 0.5 12 20 12 20 60 80 60 80 1012 200 13 12.7 2.8 4.8 9 40 5.4 26 12 9 4.7 1.6 1.3 1.6 0.8 0.7 5.0 8.0
Parameter Input Offset Voltage Input Offset Current OP15 OP17 Input Bias Current OP15 OP17 Input Resistance Large-Signal Voltage Gain Output Voltage Swing Supply Current Slew Rate2 Gain Bandwidth3 Product Closed-Loop Bandwidth Settling Time OP15
Symbol VOS IOS
Conditions RS = 50 W TJ = 25C1 Device Operating TJ = 25C1 Device Operating
Min
Max 1.0 20 40 20 50 100 200 100 250
Min
Max 3.0 50 100 50 125 200 400 200 500
Unit mV pA pA pA pA pA pA pA pA W V/mV V V mA mA V/ms V/ms MHz MHz MHz MHz ms ms ms ms ms ms V dB dB mV/V mV/V nV//Hz nV//Hz pA//Hz pA//Hz pF
IB TJ = 25C1 Device Operating TJ = 25C1 Device Operating RIN AVO VO ISY SR GBW CLBW tS To 0.01% To 0.05% To 0.10% To 0.01% To 0.05% To 0.10% IVR CMRR PSRR en in CIN VCM = 10.5 V VCM = 10.3 V VS = 10 V to 18 V VS = 10 V to 18 V fO = 100 Hz fO = 1 kHz fO = 100 Hz fO = 1 kHz 10.5 86 RL 2 kW VO = 10 V RL = 10 kW RL = 2 kW OP15 OP17 AVCL = 1, OP15 AVCL = 5, OP17 OP15 OP17 AVCL = 1, OP15 AVCL = 5, OP17 10 45 4.0 20 100 12 11
240 13 12.7 2.7 4.6 13 60 6.0 30 14 11 4.5 1.5 1.2 1.5 0.7 0.6
OP17
Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Noise Voltage Density Input Noise Current Density Input Capacitance
NOTES 1 Input bias current is specified for two different conditions. The T J = 25C specification is with the junction at ambient temperature; the device operating specification is with the device operating in a warmed-up condition at 25C ambient. The warmed-up bias current value is correlated to the junction temperature value via the curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and IOS are measured at VCM = 0. 2 Settling time is defined here for a unity gain inverter connection using 2 k W resistors. It is the time required for the error voltage (the voltages at the inverting input pit on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See settling time test circuit. 3 Sample tested. 4 Settling time is defined here for A V = -5 connection with RF = 2 kW. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 2 V step input is applied to the inverter. See settling time test circuit.
-2-
REV. A
OP15/OP17 Electrical Characteristics (@ V = 15 V, -55 C T 125 C, unless otherwise noted.)
S A
Parameter Input Offset Voltage Average Input Offset Voltage Drift Without External Trim With External Trim Input Offset Current2 OP17 Input Bias Current2 OP17 Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing
1
Symbol VOS TCVOS TCVOS IOS IB IVR CMRR PSRR AVO VO
Conditions RS = 50 W
Min
Typ 0.4 2 2 0.6 1.0 1.2 2.0
Max 0.9 5 4.0 8.5 5.0 11
Units mV mV/C mV/C nA nA nA nA V
RP = 100 W TJ = 125C TA = 125C, device operating TJ = 125C TA = 125C, device operating 10.4 VCM = 10.4 V VS = 10 V to 18 V RL 2 kW, VO = 10 V RL 10 kW 35 12 85
97 15 120 13 57
dB mV/V V/mV V
NOTES 1 Sample tested. 2 Input bias current is specified for two different conditions. The T J = 25C specification is with the junction at ambient temperature; the device operating specification is with the device operating in a warmed-up condition at 25C ambient. The warmed-up bias current value is correlated to the junction temperature value via the curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and IOS are measured at VCM = 0.
ELECTRICAL CHARACTERISTICS unless otherwise noted)
Parameter Input Offset Voltage Symbol VOS Conditions RS = 50 W 0.3
(@ VS =
15 V, 0 C TA 70 C for E and F grades, -40 C TA 85 C for G grades
OP15F/OP17F Min Typ Max 0.55 1.5 OP15G/OP17G Min Typ Max 0.7 3.8
OP15E/OP17E Min Typ Max 0.75
Unit mV
Average Input Offset Voltage Drift1 Without External Trim TCVOS With External Trim TCVOSn Input Offset Current2 IOS OP15 OP17 Input Bias Current2 OP15 OP17 Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing IVR CMRR PSRR AVO VO IB
RP = 100 W TJ = 70C TA = 70C, Device Operating TJ = 70C TA = 70C, Device Operating TJ = 70C TA = 70C, Device Operating TJ = 70C TA = 70C, Device Operating 10.4 VCM = 10.4 V VCM = 10.25 V VS = 10 V to 18 V VS = 10 V to 15 V RL 2 kW VO = 10 V RL 10 kW 65 12 85
2 2 0.04 0.06 0.04 0.07 0.10 0.13 0.10 0.15
5 0.30 0.55 0.30 0.70 0.40 0.75 0.40 0.90 10.4
3 3 0.06 0.08 0.06 0.10 0.12 0.16 0.12 0.20
10 0.45 0.80 0.45 1.1 0.60 1.1 0.60 1.4 10.25
4 4 0.08 0.10 0.08 0.15 0.14 0.19 0.14 0.25
30 0.85 1.2 0.85 1.7 0.80 1.5 0.80 2.0
mV/C mV/C nA nA nA nA nA nA nA nA V
98 13 200 13 57
85
96 80 13 57 20 100 35 12 160 13 94
dB dB mV/V mV/V V/mV V
50 12
180 13
NOTES 1 Sample tested. 2 Input bias current is specified for two different conditions. The T J = 25C specification is with the junction at ambient temperature; the device operating specification is with the device operating in a warmed-up condition at 25C ambient. The warmed-up bias current value is correlated to the junction temperature value via the curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and IOS are measured at VCM = 0.
REV. A
-3-
OP15/OP17-SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage All Devices Except C, G (Packaged) and GR Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 V C, G (Packaged) and GR Grades . . . . . . . . . . . . . . . . 18 V Operating Temperature A Grade . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C E, F Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C G Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . All Devices Except C, G Grades . . . . . . . . . . . . . . . . 40 V C, G Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V Input Voltage2 All Devices Except C, G Grades . . . . . . . . . . . . . . . . 20 V C, G Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Input Voltage OP15E, OP15F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V OP15G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V OP17A, OP17E, OP17F . . . . . . . . . . . . . . . . . . . . . . 20 V OP17G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Output Short-Circuit Duration Indefinite Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300C
NOTES *Absolute Maximum Ratings apply to packaged parts, unless otherwise noted.
Package Type 8-Lead Hermetic DIP (Z) 8-Lead SO (S) TO-99 (J)
*
JA*
JC
Unit C/W C/W C/W
148 158 150
16 43 18
JA is specified for worst-case mounting conditions, i.e., JA is specified for device in socket for CERDIP and PDIP packages; JA is specified for device soldered to printed circuit board for SO packages.
+20V 10k
2 +3V 300 3
7 8 4 -20V 10k
Figure 2. Burn-In Circuit
8-Lead CERDIP (Z-Suffix)
BAL -IN +IN V- 1 2 3 4 8 NC 7 V+ 6 OUT 5 BAL BAL -IN +IN V-
8-Lead SOIC (S-Suffix)
1 2 3 4 8 NC 7 V+ 6 OUT 5 BAL
8-Lead TO-99 (J-Suffix)
ORDERING GUIDE
TA = 25C VOS MAX (mV) 0.5 1.0 3.0
Package Options TO-99 OP17EJ OP15FJ* OP17FJ OP15GJ* CERDIP OP15EZ OP17EZ OP15FZ* OP17FZ OP15GZ* OP17GZ OP15GS* SOIC
Operating Temperature Range COM COM XIND
For military processed devices, please refer to the Standard Microcircuit Drawing (SMD) available at www.dscc.dl.mil/programs/milspec/default.asp. SMD Part Number 5962-8954201GA* 5962-8954201PA* 5962-8954301GA* 5962-8954301PA* ADI Equivalent OP15AJMDA OP15AZMDA OP16AJMDA OP16AZMDA
*Not recommended for new designs. Obsolete April 2002.
-4-
REV. A
Typical Performance Characteristics -OP15/OP17
30 VS = 15V 27
PEAK-TO-PEAK OUTPUT SWING - V
100 WARMED-UP IN FREE AIR VS = 15V TA = 25 C
-55 C 21 +25 C 18 15 +125 C 12 9 6 3 0 100 1k 10k OUTPUT LOAD RESISTANCE - 100k
INPUT BIAS CURRENT - pA
24
80
60 a. UNDERCANCELLED IB = +16pA @ V CM = 0 b. PERFECTLY CANCELLED IB = 0pA @ V CM = 0 c. UNDERCANCELLED IB = -16pA @ V CM = 0
40
20
a b c
0
-20 -12 -10
-8
-6 -4 -2 0 2 4 6 INPUT COMMON-MODE VOLTAGE - V
8
10
12
TPC 1. Maximum Output Swing vs. Load Performance
TPC 4. Input Bias Current vs. Common-Mode Voltage
20
1M
TA = 25 C
COMMON-MODE INPUT VOLTAGE RANGE - V
RL = 2k
OPEN-LOOP VOLTAGE GAIN - V/V
500k 400k 300k 200k
15
-55 C
25 C 125 C
10
100k
5
POSITIVE FROM -55 C TO -125 C CHANGE IN CMVR IS < 0.2V NEGATIVE
0
10k
0 5 10 SUPPLY VOLTAGE - V 15 20
5
10 15 SUPPLY VOLTAGE - V
20
TPC 2. Common-Mode Input Voltage Range vs. Supply Voltage
TPC 5. Open-Loop Voltage Gain vs. Supply Voltage
1k TA = 25 C VS = 15V 100Hz < f < 10kHz 10Hz < f < 10kHz FOR RS > 4M a AMPLIFIER NOISE b JOHNSON RESISTOR NOISE c AMPLIFIER NOISE MEASURED WITH SOURCE RESISTOR c b
40 RL = 2k TA = 25 C 30
INPUT NOISE VOLTAGE -
V
100
10
PEAK-TO-PEAK OUTPUT SWING - V
20
1
10
0.1 a 0.01 100k
0
1M 10M 100M SOURCE RESISTANCE - 1G 10G
0
5
10 SUPPLY VOLTAGE - V
15
20
TPC 3. Voltage Noise vs. Source Resistance
TPC 6. Output Voltage Swing vs. Supply Voltage
REV. A
-5-
OP15/OP17
9
1n VS = 15V TA = 25 C ISY = 4.0mA FOR MAX CURVES 2.5mA FOR TYP CURVES
INPUT BIAS CURRENT - A
NULLED OFFSET VOLTAGE DRIFT - V/ C
7
5
VOS
155A MAX OP15A MAX 100p 155A TYP
3
1 TYPICAL DRIFT BAND -1
-3
OP15 TYP
-5 10k 100k RP-TRIMMING POTENTIOMETER VALUE - 1M
10p 0 20 40 60 80 100 TIME AFTER POWER APPLIED - s 120 140
TPC 7. Nulled Offset Voltage Drift vs. Potentiometer Size
TPC 10. OP15 Bias Current vs. Time in Free Air
6 VS = 15V 4
1n
156A/157A MAX
2
INPUT BIAS CURRENT - A
OFFSET VOLTAGE - mV
156A/157A TYP 100p OP17A MAX VS = 15V TA = 25 C ISY = 6.7mA FOR MAX CURVES 5.0mA FOR TYP CURVES
0
-2
-4 OP17A TYP -6 -50 -25 0 25 50 75 100 125 10p 0 20 40 60 80 100 TIME AFTER POWER APPLIED - s 120 140
TEMPERATURE - C
TPC 8. Offset Voltage Drift vs. Temperature of Representative Units
TPC 11. OP17 Bias Current vs. Time in Free Air
100n
100n VS = 15V UNITS ARE WARMED UP
INPUT BIAS CURRENT - A
155A MAX
155A MAX
INPUT BIAS CURRENT - A
10n 155A TYP OP15A MAX 1n OP15A TYP
10n 155A TYP OP15A MAXP
1n OP15 TYP
100p
100p
10p 10
30
50
70
90
110
130
150
10p 10
30
50
70
90
110
130
150
AMBIENT TEMPERATURE - C
AMBIENT TEMPERATURE - C
TPC 9. Input Bias Current vs. Ambient Temperature (Units Warmed Up in Free Air)
TPC 12. OP15 Input Bias Current vs. Ambient Temperature (Units Warmed Up in Free Air)
-6-
REV. A
OP15/OP17
100n 156A/157A MAX 0 0 0 OP17A MAX
VOLTAGE - 5V/DIV
INPUT BIAS CURRENT - A
10n 156A/157A TYP
0 0 0 0 0
1n
OP17A TYP 100p
10p 10
30
50
70
90
110
130
150
0 0 0 0 0 0 0 0 TIME - 500ns/DIV 0 0 0 0
AMBIENT TEMPERATURE - C
TPC 13. OP17 Input Bias Current vs. Ambient Temperature (Units Warmed Up in Free Air)
TPC 16. OP15 Large Signal Transient Response
3.5
0 0
SUPPLY CURRENT - mA
3.0
VOLTAGE - 20mV/DIV
0 0 0 0 0 0
2.5
-55 C 25 C 125 C
2.0
1.5
0
5
10 SUPPLY VOLTAGE - V
15
20
0 0 0 0 0 0 0 0 TIME - 100ns/DIV 0 0 0 0
TPC 14. OP15 Supply Current vs. Supply Voltage
TPC 17. OP15 Small Signal Transient Response
5.5
10
SUPPLY CURRENT - mA
5.0
OUTPUT VOLTAGE SWING FROM 0V - V
VS = 15V TA = 25 C 10mV AV = -1 5
5mV
1mV
4.5 -55 C 25 C 4.0 125 C
0
-5
10mV 3.5 0 5 10 SUPPLY VOLTAGE - V 15 20 -10 0 0.5
5mV 1.0 1.5 SUPPLY VOLTAGE - V
1mV 2.0 2.5
TPC 15. OP17 Supply Current vs. Supply Voltage
TPC 18 OP15 Settling Time
REV. A
-7-
OP15/OP17
18
16
PHASE MARGIN = 86
12
VOLTAGE GAIN - dB
120
PHASE SHIFT - Degrees
PEAK-TO-PEAK OUTPUT SWING - V
14
90 VS = 15V 100 TA = 25 C 110
28 VS = 15V TA = 25 C AV = 1
24 20 16 12 8
10
8
130 140
6
4
AV > 10
150 160 170 180 190 200
2
0
-2
-4
-6
-8
AV = 1
4 0 100k
-10 1M
10M FREQUENCY - MHz
100M
1M FREQUENCY - MHz
10M
TPC 19. OP15 Closed-Loop Bandwidth and Phase vs. Frequency
TPC 22. OP15 Maximum Output Swing vs. Frequency
28 VS = 15V 24 BANDWIDTH VARIATION FROM 5V < VS < 20V IS < 5 %
SLEW RATE - V/ sec
70 VS = 15V 60 AV = 1
BANDWIDTH - MHz
20
50 NEGATIVE 40
16
CLOSED-LOOP BANDWIDTH AV = 1
12 GAIN BANDWIDTH PRODUCT 8
30
20 POSITIVE
4 0 -50
10 0 -50
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE - C
AMBIENT TEMPERATURE - C
TPC 20. OP15 Bandwidth vs. Temperature
TPC 23. OP15 Slew Rate vs. Temperature
120
100
COMMON-MODE REJECTION RATIO - dB
VS = 15V TA = 25 C
100
VS = 15V TA = 25 C 80
OPEN-LOOP VOLTAGE GAIN - dB
80
60
60
40
40
20
20
0 -20
1
10
100
1k 10k 100k FREQUENCY - Hz
1M
10M
100M
0
1
10
100
1k 10k 100k FREQUENCY - Hz
1M
10M
100M
TPC 21. OP15 Open-Loop Gain vs. Frequency
TPC 24. OP15 Common-Mode Rejection Ratio vs. Frequency
-8-
REV. A
OP15/OP17
120
POWER SUPPLY REJECTION RATIO - dB
0
TA = 25 C
0
100
0
80 POSITIVE SUPPLY 60 NEGATIVE SUPPLY 40
VOLTAGE - 5V/DIV
0 0 0 0
20
0
0 10
100
1k
10k 100k FREQUENCY - Hz
1M
10M
0 0 0 0 0 0 0 0 TIME - 200ns/DIV 0 0 0 0
TPC 25. OP15 Power Supply Rejection Ratio vs. Frequency
TPC 28. OP17 Large Signal Transient Response
100 VS = 15V TA = 25 C
0 0 0
AV = 100
OUTPUT IMPEDANCE -
10
VOLTAGE - 20mV/DIV
0 0 0 0 0
AV = 10 AV = 1 1
0 1k
10k
100k FREQUENCY - Hz
1M
10M
0 0 0 0 0 0 0 0 TIME - 100ns/DIV 0 0 0 0
TPC 26. OP15 Output Impedance vs. Frequency
TPC 29. OP17 Small Signal Transient Response
140
OUTPUT VOLTAGE SWING FROM 0V - V
10
VOLTAGE NOISE DENSITY - nV/ Hz
120
VS = 15V TA = 25 C
10mV 5
5mV
1mV
VS = 15V TA = 25 C AV = -5
100
80
0
60 l/f CORNER FREQUENCY 40
-5 10mV 5mV 1mV
20 0 1k
10k
100k FREQUENCY - Hz
1M
10M
-10
0
0.5
1.0 1.5 SUPPLY VOLTAGE - V
2.0
2.5
TPC 27. OP15 Voltage Noise Density vs. Frequency
TPC 30. OP17 Settling Time
REV. A
-9-
OP15/OP17
28 POWER SUPPLY REJECTION RATIO - dB VS = 15V TA = 25 C AV = 5
120 TA = 25 C 100 POSITIVE SUPPLY 80
PEAK-TO-PEAK OUTPUT SWING - V
24 20 16 12 8
60 NEGATIVE SUPPLY 40
4 0 100k
20
1M FREQUENCY - MHz
10M
0 10
100
1k
10k 100k FREQUENCY - Hz
1M
10M
TPC 31. OP17 Maximum Output Swing vs. Frequency
TPC 34. OP17 Power Supply Rejection Ratio vs. Frequency
110 NEGATIVE 100 VS = 15V AV = 5
100
VS = 15V TA = 25 C
SLEW RATE - V/ sec
OUTPUT IMPEDANCE -
90
10
AV = 100
AV = 10
80
POSITIVE
70
1.0
60
50 40 -50
-25
0
25
50
75
100
125
0 1k
10k
AMBIENT TEMPERATURE - C
100k FREQUENCY - Hz
1M
10M
TPC 32. OP17 Slew Rate vs. Temperature
TPC 35. OP17 Output Impedance vs. Frequency
100
COMMON-MODE REJECTION RATIO - dB
VS = 15V TA = 25 C 80
140 VS = 15V TA = 25 C
VOLTAGE NOISE DENSITY - nV/ Hz
120
100
60
80
40
60 l/f CORNER FREQUENCY 40
20
20 0 1k
0
1
10
100
1k 10k 100k FREQUENCY - Hz
1M
10M
100M
10k
100k FREQUENCY - Hz
1M
10M
TPC 33. OP17 Common-Mode Rejection Ration vs. Frequency
TPC 36. OP17 Voltage Noise vs. Frequency
-10-
REV. A
OP15/OP17
TEST CIRCUITS
V+
2k 0.1% +15V 10V
100k 7
0V 1k 0.1% -15V
400 0.1%
2
7
2 3
1
5
6
OP17
3 4
6
2N4416 100pF 3k
4
VOUT
SUMMING NODE
NOTE: V OS CAN BE TRIMMED WITH POTENTIOMETERS RANGING FROM 10k TO 1M . FOR MOST UNITS TCVOS WILL BE MINIMIZED WHEN VOS IS ADJUSTED WITH A 100k POTENTIOMETER
5k 0.1%
AV = -1
SCOPE
2N4416 2k
+15V
Figure 3. Input Offset Voltage Nulling
2k 0.1% +15V 10V 0V 5k 0.1% -15V SUMMING NODE 5k 0.1% 2k 0.1%
Figure 6. OP17 Settling Time Test Circuit
APPLICATION INFORMATION Dynamic Operating Considerations
6 2N4416 100pF 3k AV = -1
2
7
OP15
3 4
VOUT
As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize "pick-up" and maximize the frequency of the feedback pole by minimizing the capacitance for the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to ac ground set the frequency of this pole. In many instances the frequency of this pole is much greater than the expected, 3 dB frequency of the close-loop gain, and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency, a lead capacitor should be placed from the output to the negative input of the op amp. The value of the added capacitor should be such that the RC time-constant of this capacitor and the resistance it parallels is greater than, or equal to, the original feedback pole time is constant.
R1 10k R2 5k C2 30pF
LSB
SCOPE
2N4416 2k
+15V
Figure 4. OP15 Settling Time Test Circuit
DIGITAL INPUTS +10V
MSB
+15V
RREF 5k
5
6
7
8
9
10
11 12
B1 B2 B3 B4 B5 B6 B7 B8
7
IO IO
14
VREF+
4
2
15
VREF-
DAC08E
V-
13
OP15F
2 3
6
VO = 0V TO 10V 4
V+
3
CC
C1 0.1 F
16
VLC
1
+15V
-15V
-15V
Figure 5. Current-to-Voltage Amplifier Output
REV. A
-11-
OP15/OP17
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches).
8-Lead Ceramic Dip - Glass Hermetic Seal [CERDIP] (Q-8)
0.13 (0.0051) 1.40 (0.0551) MAX MIN
8 5
8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8)
5.00 (0.1968) 4.80 (0.1890)
8 5 4
PIN 1
1 4
7.87 (0.3089) 5.59 (0.2201)
4.00 (0.1574) 3.80 (0.1497) PIN 1
1
6.20 (0.2440) 5.80 (0.2284)
2.54 (0.1000) BSC 10.29 (0.4051) MAX 5.08 (0.2000) MAX 5.08 (0.2000) 3.18 (0.1252) 0.58 (0.0228) 0.36 (0.0142) 1.52 (0.0600) 0.38 (0.0150) 3.81 (0.1500) MIN SEATING 1.78 (0.0701) PLANE 0.76 (0.0299) 15 0 0.38 (0.0150) 0.20 (0.0079) 8.13 (0.3201) 7.37 (0.2902)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE
1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.19 (0.0075)
0.50 (0.0196) 0.25 (0.0099)
45
0.51 (0.0201) 0.33 (0.0130)
1.27 (0.0500) 0.41 (0.0160)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA
8-Lead Metal Can [TO-99] (H-08)
REFERENCE PLANE 4.70 (0.1850) 4.19 (0.1650) 12.70 (0.5000) MIN 6.35 (0.2500) MIN 1.27 (0.0500) MAX 5 9.40 (0.3700) 8.51 (0.3350) 8.51 (0.3350) 7.75 (0.3050) 4 5.08 (0.2000) BSC 3 2 0.48 (0.0190) 0.41 (0.0160) 0.53 (0.0210) 0.41 (0.0160) BASE & SEATING PLANE 2.54 (0.1000) BSC 1 0.86 (0.0340) 0.71 (0.0280) 45 BSC 8 6 7 1.14 (0.0450) 0.69 (0.0270) 2.54 (0.1000) BSC 4.06 (0.1600) 3.56 (0.1400)
1.02 (0.0400) MAX 1.02 (0.0400) 0.25 (0.0100)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
COMPLIANT TO JEDEC STANDARDS MO-002AK
9/02--Data Sheet changed from REV. 0 to REV. A.
Deleted OP16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Deleted 12 TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -12- REV. A
PRINTED IN U.S.A.
Page
C02789-0-9/02(A)

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